1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to a method of manufacturing a two-power supply voltage compatible CMOS semiconductor device in which the number of photolithography steps for forming an LDD, a pocket, and a source/drain region can be reduced as compared with the prior art.
2. Description of the Prior Art
As a CMOS semiconductor device is more and more micropatterned, its gate length decreases. Accordingly, it is indispensable to suppress a decrease in threshold voltage, i.e., a so-called short-channel effect, and a degradation in hot carriers of mainly an n-type MOSFET. For this purpose, the power supply voltage must be decreased.
In the circuit configuration, it is also necessary to form a MOSFET compatible with the previous-generation power supply voltage at the interface with an external circuit.
From the above reasons, in a CMOS semiconductor device, MOSFETs each compatible with two different power supply voltages, i.e., four types of MOSFETs including a low power supply voltage compatible n-type MOSFET, a low power supply voltage compatible p-type MOSFET, a high power supply voltage compatible n-type MOSFET, and a high power supply voltage compatible p-type MOSFET, must be formed separately on the wafer. Items required for the four types of MOSFETs are as follows.
Since a low power supply voltage compatible MOSFET portion is expected to operate at a high speed, a device must have a small gate length and a high drive capability. Accordingly, a structure capable of suppressing the short-channel effect and having a low parasitic resistance for increasing the drive capability is required.
Since a high power supply voltage compatible MOSFET portion is generally used at only the interface with an external circuit, its drive capability does not matter. Accordingly, a MOSFET having a large gate length is generally used, and suppression of the short-channel effect does not generally become an issue. Since the power supply voltage is high, a degradation in reliability such as hot carrier resistance, and suppression of the junction leakage current between the source/drain and the well pose problems.
Even if the low power supply voltage compatible MOSFET and the high power supply voltage compatible MOSFET are formed on the same wafer, they require separate LDD structures and source/drain structures.
More specifically, low power supply voltage compatible n- and p-type MOSFETs preferably have structures each employing both a comparatively heavily doped LDD layer and a pocket layer in order to satisfy both suppression of the short-channel effect and decrease in parasitic resistance. A high power supply voltage compatible n-type MOSFET must have a lightly doped LDD structure in order to improve the hot carrier resistance. A high power supply voltage compatible p-type MOSFET must have a structure that can suppress the leakage current between the source/drain and the well.
A conventional method of manufacturing a CMOS semiconductor device compatible with two different power supply voltages will be described with reference to FIGS. 1A to 1H. As this prior art, a case wherein the low power supply voltage is 1.8 V and the high power supply voltage is 3.3 V will be described. In the description, the gate length of the 1.8 -V compatible MOSFET is 0.18 .mu.m as the typical example, and the gate length of the 3.3 -V compatible MOSFET is 0.35 .mu.m as the typical example.
As shown in FIG. 1A, isolation regions 2, n-type well regions 3, and p-type well regions 4 are formed in a semiconductor substrate 1. After that, 1.8 -V power supply voltage compatible thin gate oxide films 5 and 3.3 -V power supply voltage compatible thick gate oxide films 6 are formed.
The gate oxide films 5 and 6 having the two different thicknesses are usually formed in the following manner. A gate oxide film having an appropriate thickness is formed once, and only its 1.8 -V power supply voltage portion is wet-etched to remove the gate oxide film. After that, gate oxidation is performed again for a thickness matching the design of the 1.8 -V power supply voltage portion. The 3.3 -V power supply voltage portion is subjected to gate oxidation twice. The thickness of the first gate oxidation is adjusted so that a gate oxide film having a 3.3 -V power supply voltage compatible thickness is formed (not shown). After that, a gate electrode material is deposited, and photolithography and etching are performed to form gate electrodes 7.
After that, as shown in FIG. 1B, a portion of the substrate 1 other than a prospective 1.8 -V power supply voltage compatible n-type MOSFET formation region 11 is masked with resists 12 (first photolithography step), and an n-type impurity, e.g., As.sup.+ 13, is ion-implanted at a comparatively high concentration to form an n-type LDD region 14. After that, a p-type impurity, e.g., BF.sub.2.sup.+ 15, is obliquely ion-implanted to form a p-type pocket region 16.
The 1.8 -V power supply voltage compatible n-type MOSFET is a micropatterned portion having a gate length of 0.18 .mu.m, and it needs a decrease in parasitic resistance and suppression of the short-channel effect. The former is realized by setting the n-type LDD region to have a comparatively high As concentration on the order of about 10.sup.19 cm.sup.-3. The latter is realized by setting the pocket region to have a boron concentration on the order of about 10.sup.18 cm.sup.-3.
The resists 12 are removed. As shown in FIG. 1C, a portion of the substrate 1 other than a prospective 1.8 -V power supply voltage compatible p-type MOSFET formation region 17 is masked with resists 18 (second photolithography step). After that, a p-type impurity, e.g., BF.sub.2.sup.+ 19, is ion-implanted at a comparatively high concentration to form a p-type LDD region 20. Then, an n-type impurity, e.g., As.sup.+ 21, is obliquely ion-implanted to form an n-type pocket region 22.
The 1.8 -V power supply voltage compatible p-type MOSFET is a micropatterned portion having a gate length of 0.18 .mu.m, and it needs a decrease in parasitic resistance and suppression of the short-channel effect. The former is realized by setting the p-type LDD region to have a comparatively high boron concentration on the order of about 10.sup.19 cm.sup.-3. The latter is realized by setting the pocket region to have an As concentration on the order of about 10.sup.18 cm.sup.-3.
The resists 18 are removed. As shown in FIG. 1D, a portion of the substrate 1 other than a prospective 3.3 -V power supply voltage compatible n-type MOSFET formation region 23 is masked with resists 24 (third photolithography step). After that, an n-type impurity, e.g., P.sup.+ 25, is ion-implanted at a comparatively low concentration to form an n-type LDD region 26.
The 3.3 -V power supply voltage compatible n-type MOSFET is a region having a large gate length of 0.35 .mu.m, and a short-channel effect does not occur. Accordingly, pocket implantation is not necessary. Since this region has a large gate length, its parasitic resistance does not pose a problem.
Since the power supply voltage is high, the hot carrier must be suppressed. Accordingly, the n-type LDD region 26 must be formed by using broad-profile P.sup.+ 25 to a low concentration on the order of about 10.sup.18 cm.sup.-3.
The resists 24 are removed. As shown in FIG. 1E, a portion of the substrate 1 other than a prospective 3.3 -V power supply voltage compatible p-type MOSFET formation region 27 is masked with resists 28 (fourth photolithography step). After that, a p-type impurity, e.g., BF.sub.2.sup.+ 29, is ion-implanted to form a p-type LDD region 30.
The 3.3 -V power supply voltage compatible p-type MOSFET is a region having a large gate length of 0.35 .mu.m, and a short-channel effect does not occur. Accordingly, pocket implantation is not necessary. If pocket implantation is performed, the junction leakage current between the source/drain region and the well region increases. Thus, pocket implantation is not preferably performed.
The resists 28 are removed, and side walls 31 composed of oxide films are formed, as shown in FIG. 1F.
After that, as shown in FIG. 1G, the prospective 1.8 -V power supply voltage compatible p-type MOSFET formation region 17 and prospective 3.3 -V power supply voltage compatible p-type MOSFET formation region 27 are masked with resists 32 (fifth photolithography step), and an n-type impurity, e.g., As.sup.+ 33, is ion-implanted at a high concentration to form n-type source/drain regions 34.
The resists 32 are removed. As shown in FIG. 1H, the prospective 1.8 -V power supply voltage compatible n-type MOSFET formation region 11 and prospective 3.3 -V power supply voltage compatible n-type MOSFET formation region 23 are masked with resists 35 (sixth photolithography step), and a p-type impurity, e.g., B.sup.+ 36, is ion-implanted at a high concentration to form p-type source/drain regions 37.
The resists 35 are removed, and the source/drain regions are annealed for activation. After that, a silicide layer, an interlevel insulating film, interconnections, and the like are formed to complete a CMOS semiconductor device.
According to the prior art shown in FIGS. 1A to 1H, since the 1.8 -V power supply voltage compatible n-type MOSFET and the 1.8 -V power supply voltage compatible p-type MOSFET have comparatively heavily doped LDD regions, they can sufficiently decrease the parasitic resistance to allow expectation for a high drive current. Since these MOSFETs have pocket structures, they can sufficiently suppress the short-channel effect even at a microregion having a gate length of 0.18 .mu.m. Since the 3.3 -V power supply voltage compatible n-type MOSFET uses low-concentration, broad-profile phosphor to form the LDD, it can sufficiently suppress the hot-carrier effect even when a high power supply voltage of 3.3 V is used. The 3.3 -V power supply voltage compatible p-type MOSFET does not have a pocket region, unlike the 1.8 -V power supply voltage compatible p-type MOSFET. Thus, the junction leakage current between the source/drain region and the well region does not increase even when a high power supply voltage of 3.3 V is used.
In this manner, according to the method of manufacturing a two-power supply voltage compatible CMOS semiconductor device shown in FIGS. 1A to 1H, the optimum LDD, pocket, and source/drain structure can be formed in the four types of MOSFETs. On the other hand, however, photolithography is required a total of six times to form the LDDs, pockets, and source/drain regions. This is because, since separate LDD structures are formed for the low power supply voltage portions and the high power supply voltage portions, photolithography must be performed separately for the separate LDD structures. The increase in number of photolithography steps leads to an increase in manufacturing cost, and must be solved by all means.
Another conventional method of manufacturing a CMOS semiconductor device compatible with two different power supply voltages will be described with reference to FIGS. 2A to 2H. As this prior art, a case wherein the low power supply voltage is 1.8 V and the high power supply voltage is 3.3 V will be described. In the description, the gate length of the 1.8 -V power supply compatible MOSFET is 0.18 .mu.m as the typical example, and the gate length of the 3.3 -V power supply compatible MOSFET is 0.35 .mu.m as the typical example.
As shown in FIG. 2A, isolation regions 52, n-type well regions 53, and p-type well regions 54 are formed in a semiconductor substrate 51. After that, 1.8 -V power supply voltage compatible thin gate oxide films 55 and 3.3 -V power supply voltage compatible thick gate oxide films 56 are formed.
The gate oxide films 55 and 56 having the two different thicknesses are usually formed in the following manner. A gate oxide film having an appropriate thickness is formed once, and only its 1.8 -V power supply voltage portion is wet-etched to remove the gate oxide film. After that, gate oxidation is performed again for a thickness matching the design of the 1.8 -V power supply voltage portion. The 3.3 -V power supply voltage portion is subjected to gate oxidation twice. The thickness of first gate oxidation is adjusted so that a gate oxide film having a 3.3 -V power supply voltage compatible thickness is formed (not shown). After that, a gate electrode material is deposited, and photolithography and etching are performed to form gate electrodes 57.
After that, as shown in FIG. 2B, a portion of the substrate 51 other than a prospective 1.8 -V power supply voltage compatible n-type MOSFET formation region 61 is masked with resists 62 (first photolithography step), and an n-type impurity, e.g., As.sup.+ 63, is ion-implanted at a comparatively high concentration to form an n-type LDD region 64. After that, a p-type impurity, e.g., BF.sub.2.sup.+ 65, is obliquely ion-implanted to form a p-type pocket region 66.
The 1.8 -V power supply voltage compatible n-type MOSFET is a micropatterned portion having a gate length of 0.18 .mu.m, it needs a decrease in parasitic resistance and suppression of the short-channel effect. The former is realized by setting the n-type LDD region to have a comparatively high As concentration on the order of about 10.sup.19 cm.sup.-3. The latter is realized by setting the pocket region to have a boron concentration on the order of about 10.sup.16 cm.sup.-3.
The resists 62 are removed. As shown in FIG. 2C, a portion of the substrate 51 other than a prospective 1.8 -V power supply voltage compatible p-type MOSFET formation region 67 is masked with resists 68 (second photolithography step). After that, a p-type impurity, e.g., BF.sub.2.sup.+ 69, is ion-implanted at a comparatively high concentration to form a p-type LDD region 70. Then, an n-type impurity, e.g., As.sup.+ 71, is obliquely ion-implanted to form an n-type pocket region 72.
The 1.8 -V power supply voltage compatible p-type MOSFET is a micropatterned portion having a gate length of 0.18 .mu.m, and it needs a decrease in parasitic resistance and suppression of the short-channel effect. The former is realized by setting the p-type LDD region to have a comparatively high boron concentration on the order of about 10.sup..multidot. cm.sup.-3. The latter is realized by setting the pocket region to have an As concentration on the order of about 10.sup..about. cm.sup.-3.
The resists 68 are removed, and side walls 73 composed of oxide films are formed, as shown in FIG. 2D.
After that, as shown in FIG. 2E, a portion of the substrate 51 other than the prospective 1.8 -V power supply voltage compatible n-type MOSFET formation region 61 is masked with resists 74 (third photolithography step), and an n-type impurity, e.g., As.sup.+ 75, is ion-implanted to a high concentration to form an n-type source/drain region 76.
The resists 74 are removed. As shown in FIG. 2F, a portion of the substrate 51 other than the prospective 1.8 -V power supply voltage compatible p-type MOSFET formation region 67 is masked with resists 77 (fourth photolithography step), and a p-type impurity, e.g., B.sup.+ 78, is ion-implanted at a high concentration to form a p-type source/drain region 79.
The resists 77 are removed. As shown in FIG. 2G, a portion of the substrate 51 other than a prospective 3.3 -V power supply voltage compatible n-type MOSFET formation region 80 is masked with resists 81 (fifth photolithography step), and n-type impurities, e.g., P.sup.+ 82 and As.sup.+ 83, are ion-implanted to form a DDD structure, having a comparatively lightly doped, broad-profile phosphorus region 85, outside an n-type As source/drain region 84.
The resists 81 are removed. As shown in FIG. 2H, a portion of the substrate 51 other than a prospective 3.3 -V power supply voltage compatible p-type MOSFET formation region 87 is masked with resists 88 (sixth photolithography step), and a p-type impurity, e.g., B.sup.+ 89, is ion-implanted at a high concentration to form a p-type source/drain region 90.
The resists 88 are removed, and the source/drain regions are annealed for activation. After that, a silicide layer, an interlevel insulating film, interconnections, and the like are formed to complete a CMOS semiconductor device.
According to the prior art shown in FIGS. 2A to 2H, since the 1.8 -V power supply voltage compatible n-type MOSFET and the 1.8 -V power supply voltage compatible p-type MOSFET have comparatively heavily doped LDD regions, they can sufficiently decrease the parasitic resistance to allow expectation for a high drive current. Since these MOSFETs have pocket structures, they can sufficiently suppress the short-channel effect even at a microregion having a gate length of 0.18 .mu.m. Since the 3.3 -V power supply voltage compatible n-type MOSFET uses low-concentration, broad-profile phosphorus to form the LDD, it can sufficiently suppress the hot-carrier effect even when a high power supply voltage of 3.3 V is used. The 3.3 -V power supply voltage compatible p-type MOSFET does not have a pocket region, unlike the 1.8 -V power supply voltage compatible p-type MOSFET. Thus, the junction leakage current between the source/drain region and the well region does not increase even when a high power supply voltage of 3.3 V is used.
According to the method of manufacturing a two-power supply voltage compatible CMOS semiconductor device shown in FIGS. 2A to 2H, however, photolithography is required a total of six times to form the LDDs, pockets, and source/drain regions, in the same manner as in the prior art shown in FIGS. 1A to 1H. This is because, since separate LDD structures are formed for the low power supply voltage portions and the high power supply voltage portions, photolithography must be performed separately for the separate LDD structures. The increase in number of photolithography steps leads to an increase in manufacturing cost, and must be solved by all means.
As has been described above, when forming a CMOS semiconductor device compatible with two different power supply voltages so its internal circuit operates at 1.8 V while its an interface with an external circuit operates at 3.3 V, the 1.8 -V power supply voltage compatible MOSFETs must have an LDD structure, a pocket structure, and a source/drain structure appropriate for a smaller channel length and a high ion concentration. The 3.3 -V power supply voltage compatible MOSFETs must have an LDD structure and a source/drain structure that can suppress a degradation in reliability, e.g., the hot-carrier effect.
When forming four types of MOSFETs including n-type MOSFETs and p-type MOSFETs each compatible with the two different power supply voltages, conventionally, six photolithography steps are required to form LDD regions, pocket regions, and source/drain regions that are optimum for these four types of transistors.